1. Field of the Invention
The present invention relates in general to a method of controlling the top width of a deep trench capacitor. In particular, the present invention relates to a method of preventing increased top width of a deep trench.
2. Description of the Related Art
DRAM is readable and writeable memory. Each DRAM cell consists of one transistor and one capacitor, obtaining high integrity compared with other memory types, allowing comprehensive application in computers and electronic products. Currently, plane transistors with deep trench capacitors are designed in a 3-dimensional capacitor structure for the deep trench of the semiconductor substrate, minimizing dimensions and power consumption, and accelerating operating speed.
FIG. 1a is a plane view of the deep trench in a conventional DRAM cell. In folded bit line, each active area includes two word lines (WL1 & WL2) and one bit line (BL), with BC representing a bit line contact, DT a deep trench, and the top width of the deep trench in the bit line direction.
FIG. 1b is a cross section of a deep trench capacitor in a conventional DRAM cell. A semiconductor silicon substrate 10 has a deep trench DT, the lower area of which acting as a deep trench capacitor 12, consisting of a buried plate, a node dielectric, and a storage node. In fabrication of the deep trench capacitor 12, a deep trench DT is formed in the p-type semiconductor substrate 10 using RIE, and n+-type ions are diffused into the lower area of a deep trench DT using a heavy doping oxide, such as ASG, with short duration/high temperature annealing, so that an n+-type diffusion area 14 is formed to act as the buried plate of the deep trench capacitor 12. And a silicon nitride layer 16 is formed at the inner sidewall and bottom of the deep trench DT lower area, acting as the node dielectric of the deep trench capacitor 12. Subsequently, an n+-type doped first polysilicon layer 18 is formed inside the deep trench DT, recessing the first polysilicon layer 18 at a predetermined depth to act as the storage node of the deep trench capacitor 12.
After completion of the above deep trench capacitor 12, a collar dielectric 20 is fabricated on the upper sidewalls of the deep trench DT, then a second polysilicon layer 22 and a third polysilicon layer 24 are sequentially formed on the upper deep trench DT. Subsequently, a STI structure 26, word line (WL1 & WL2), source/drain diffusion area 28, bit line contact (CB), and bit line(BL) processes are formed. The STI structure 26 is formed to isolate the adjacent two DRAM cells.
In order to connect the deep trench capacitor 12 to the surface of the transistor, the buried strap outdiffusion area 30 is formed on the silicon substrate 10 of the deep trench DT top side area, acting as an node junction, and the deep trench capacitor 12 and the above mentioned node junction 30 are connected using the second polysilicon layer 22 and the third polysilicon layer 24 formed in the deep trench DT.
For DRAM, the smaller the feature size, the more important the deep trench dimension becomes. When capacity increases with size of the deep trench DT, process tolerance of overlay with the subsequent Active Area (AA) reduces commensurately, particularly in the overlay margin area L between the source/drain diffusion area 28 and the buried strap outdiffusion area 30, in which serious current leakage results, impacting the performance of the sub-threshold voltage (Vt).
FIGS. 2a˜2f are cross sections of the conventional process of employing pullback process on the top of the deep trench, smoothing the subsequent polysilicon layer to fill the deep trench. In FIG. 2a, a formed deep trench capacitor 12 in the p-type semiconductor silicon substrate 10, comprising a collar structure 11, consists of a silicon nitride pad layer 13 and a silicon oxide pad layer 15, a deep trench 17, an n+-type diffusion area 14, a silicon nitride layer 16 and an n+-type doped first polysilicon layer 18. The silicon nitride pad layer 13 at the top of the deep trench 17 is pulled back using heated phosphoric acid, since the pullback to the silicon nitride pad layer 13 has a higher etching rate than the silicon oxide pad layer 15, the structure as in FIG. 2b is formed.
Subsequently, in FIG. 2c, the first silicon oxide layer 34 is formed on the exposed surface of the silicon substrate 10, so that the upper sidewalls of the deep trench 17 are capped, insulating the n+-type diffusion area 14 and the subsequently formed buried strap outdiffusion area 30. And in FIG. 2d, the second silicon oxide layer 36 is formed by CVD, and the portion of second silicon oxide layer 36 on the top of the first polysilicon layer 18 is removed using anisotropic dry etching.
Subsequently, in FIG. 2e, the second polysilicon layer 22 is filled into the deep trench 17, and recesses the second polysilicon layer 22 to a predetermined depth. Eventually, in FIG. 2f, a portion of the first silicon oxide layer 34 and the second silicon oxide layer 36 are removed using wet etching until the top of the second polysilicon layer 22 protrudes, and the remaining first silicon oxide layer 34 and second silicon oxide layer 36 act as a collar dielectric layer 20, effectively insulating the buried strap outdiffusion area 30 and the buried strap 14, thereby preventing current leakage.
Since a portion of the silicon substrate 10 is converted to SiO2 during the first silicon oxide layer 34 deposition, subsequent wet etching increases the top width of the deep trench DT (from S to S′), as in FIG. 3. The overlay tolerance between word line WL and deep trench DT, and the distribution of the buried strap outdiffusion area 30 are thus impacted, especially, shortening the overlay margin area L between the source/drain diffusion area 28 and the buried strap outdiffusion area 30, suffering serious current leakage, and deteriorating the performance of sub-Vt.
When pulling back the collar structure 11 at the top of the deep trench 170 to expose the silicon substrate 10 is a main focus of leading deep trench 170 top width increase, the described step is also very important. Skipping this step, the top width of the deep trench may effectively be prevented from increasing, thus suppressing sub-voltage leakage. The high (exceeding 4:1) aspect ratio of a deep trench 170 induces seam 19 or void when the second polysilicon 22 is filled into the deep trench 170 if collar structure 11 is not pulled back, as in FIG. 2g. Consequently, void or seam formed not only increases impedance of the deep trench capacitor, but also causes deep trench capacitor damage by etching solution or solvent during subsequent chemical cleaning, finally resulting in device breakdown.
Therefore, since pullback is this required, it is critical to prevent top width of a deep trench 17 from increasing.